1. Field of the Invention
The present invention relates to a memory device and a method of arranging signal and power lines.
2. Description of the Related Art
Semiconductor memory devices are typically divided into a memory cell array region and a peripheral circuit region. The memory cell array region includes sub-memory cell arrays and sense amplifier regions located adjacent to the sub-memory cell arrays. Memory cells are formed on a lower layer of the sub-memory cell arrays, and devices, such as transistors constituting a sense amplifier, a pre-charge circuit, a data input/output gate, etc., are formed on a lower layer of the sense amplifier regions. Signal and power lines are often disposed horizontally and vertically over the sense amplifier regions in two metal layers. The signal lines connect with the lower layer devices and some of the power lines through contacts.
FIG. 1 illustrates a conventional semiconductor memory device. Referring to FIG. 1, the semiconductor memory device includes a memory cell array 10, a column decoder 20, and a row decoder 30. The memory cell array 10 includes multiple sub-memory cell arrays SMCA and sub-word line drivers SWD alternately disposed in vertically columns. The memory cell array 10 includes conjunction regions CJ and sense amplifiers SA also alternately disposed in vertically columns. Each conjunction region CJ is adjacent to a sub-word line driver SWD, and each sense amplifier SA is adjacent to sub-memory cell arrays SMCA. In other words, the semiconductor memory device includes rows of alternating sub-memory cell arrays SMCA and sense amplifiers SA, and rows of alternating sub-word line drivers SWD and conjunction regions CJ.
The memory cell array 10 includes a memory cell MC connected to a sub-word line SWL and a bit line BL. During memory access operations to the memory cell MC, the column decoder 20 selects a column selection signal CSL responsive to a column address CA and the row decoder 30 selects a word line selection signal PX responsive to a row address RA. The row decoder may select a main word line (not shown) that is combined with the word line selection signal PX to access the memory cell MC. The conjunction regions CJ include control signal generation circuits for controlling a sub-word line driver SWD and a sense amplifier SA. The sense amplifier SA includes sense amplifiers, a pre-charge circuit, a data input/output gate, etc.
The semiconductor memory device includes a plurality of signal lines, such as local data input/output lines LIO and global data input/output lines GIO, and a plurality of power lines P1 and P2. Power lines P1, word selection signal line PX, and the local data input/output line LIO are configured to vertically cross over the conjunction regions CJ and the sense amplifiers SA. Power lines P2 and global data input/output lines GIO are configured to horizontally cross over the sense amplifiers SA and the sub-memory cell arrays SMCA. The power lines P2 are disposed on both sides of the global data input/output lines GIO to help ensure the stable supply of power and signals by the global data input/output lines GIO.
As the size of these semiconductor memory devices decreases, the layout area allocated for the sense amplifier SA is also reduced, thus rendering the power and signal line configuration of the semiconductor memory device difficult to implement. Furthermore, as the number of global data input/output lines GIO increases, the number of power lines P2 and contacts to the signals also increases. Accordingly, the top layout of the sense amplifiers may become significantly complicated and difficult, if not impossible, to implement.